1. Technical Field
The present invention relates to a test apparatus and a test method. In particular, the present invention relates to a test apparatus and a test method for testing a memory under test that stores data in block-units.
2. Related Art
Recently, the demand for non-volatile memories such as NAND flash memories has increased greatly. The memory blocks in such non-volatile memories have a prescribed rate of defect occurrence, such as 2%, for example. Therefore, in the design phase, the memory is provided with backup blocks in addition to a number of blocks corresponding to the set storage capacity. A test apparatus judges the acceptability of each block during manufacturing and writes, to the memory, information for disabling blocks in which a defect occurs. In this way, even a memory having up to a certain amount of defects can be treated as an acceptable memory operating correctly.
Japanese Application Publication No. 2007-12221 discloses a test apparatus for testing a flash memory or the like that uses an algorithmic pattern generator (ALPG).
A conventional test apparatus uses a bad block memory to manage information concerning which blocks have defects. The bad block memory stores data in a bit map format, and stores, in addresses having the same addresses of the blocks of the memory under test, logic values of 0 or 1 indicating whether the corresponding block is operating correctly. In order to disable a block in which a defect occurs, it is necessary for the test apparatus to supply the memory under test with the address of the block to be disabled. Therefore, in order for the test apparatus to disable a block, the bad block memory must be scanned after the test is completed, and then the test apparatus must acquire the necessary address values and accumulate these values in another storage region, and then supply the memory under test with these address values accumulated after the scanning. Such a process takes a long time, and takes an even longer time when a plurality of devices are tested in parallel because the number of steps in the after-processing increases.